Technical Reference — 21 Chapters

Memory Management Units
and TLBs

A rigorous, implementation-level guide to address translation — from foundational virtual memory concepts through AI/ML accelerator memory systems. Targets systems engineers, OS developers, hardware architects, and ML infrastructure teams.

21Chapters
224SVG Figures
3Architectures
~198KWords
x86-64 ARM64 RISC-V GPU / AI Accelerators
Chapters
01
Memory Management Basics
23 SVGs292 KB
02
Virtual Memory Concepts
10 SVGs230 KB
03
Page Table Structures and Implementation
15 SVGs288 KB
04
Translation Lookaside Buffer (TLB) - Deep Dive
11 SVGs332 KB
05
IOMMU and DMA Remapping - Deep Dive
8 SVGs350 KB
06
Memory Protection and Access Control
10 SVGs297 KB
07
Page Faults and Exception Handling
10 SVGs756 KB
08
Advanced MMU Topics - System Integration and Optimization
10 SVGs323 KB
09
Advanced Page Table Optimizations
10 SVGs350 KB
10
Hardware Accelerators and External MMU Access
8 SVGs351 KB
11
Virtual Memory Challenges in AI/ML Accelerators
13 SVGs403 KB
12
When MMU Architecture Breaks - AI at Scale
9 SVGs264 KB
13
Machine Learning for Memory Management - The False Hope
7 SVGs130 KB
14
Software-Managed Memory for AI Workloads
8 SVGs222 KB
15
Beyond Traditional MMU - Alternative Translation Architectures
9 SVGs187 KB
16
Advanced TLB Optimization Techniques
11 SVGs215 KB
17
Page Table Walker Microarchitecture
11 SVGs183 KB
18
MMU-Level Vulnerabilities: Spectre, Meltdown, and Paging Exploits
12 SVGs206 KB
19
CXL and the Disaggregated Address Space
13 SVGs198 KB
20
Confidential Computing and the Untrusted Hypervisor
8 SVGs125 KB
21
Hardware Memory Safety — CHERI, MTE, and Capability-Based Addressing
8 SVGs127 KB
Reading Paths
🖥️

Systems / OS Developers

Chapters 1–9 form a complete foundation covering paging, faults, reclaim, and optimizations. Chapter 19 extends this to CXL-attached memory.

⚙️

Hardware Architects

Chapters 4, 5, 10, 15, 16, 17, 18 cover translation hardware, IOMMUs, advanced TLB design, PTW microarchitecture, and paging-level vulnerabilities. Chapter 19 covers CXL disaggregation.

🤖

AI/ML Infrastructure

Chapters 11–14 address GPU and accelerator memory, LLM serving, and ML-based optimization. Chapter 20 covers confidential computing for AI workloads. Chapter 21 covers hardware memory safety relevant to AI system integrity.

🔒

Security Researchers

Chapter 6 covers the full protection model; Chapters 5 and 12 cover device and multi-tenant isolation; Chapter 18 covers MMU-level vulnerabilities including Meltdown, Spectre, L1TF/Foreshadow, and MDS in depth; Chapter 20 covers confidential computing, TDX, SEV-SNP, and ARM CCA; Chapter 21 covers hardware memory safety — CHERI, ARM MTE, and capability-based addressing.

Architecture Coverage
Processor Family Key Structures Covered
x86-64 (Intel / AMD) CR3, PML4/PDPT/PD/PT, PCID, INVPCID, INVLPG, KPTI, SGX, VT-d, EPT, AMD NPT
ARM64 (ARMv8 / v9) TTBR0/TTBR1_EL1, ASID, TLBI, TrustZone, Stage-2 (IPA→PA), SMMUv3
RISC-V satp, Sv39/Sv48/Sv57, ASID, SFENCE.VMA, VMID in hgatp, G-stage translation
GPU / AI Accelerators NVIDIA UVM, NVLink/NVSwitch peer-to-peer, TPU HBM, Intel Gaudi2, PagedAttention

Format

Each chapter is a self-contained HTML file with:

  • All SVG diagrams embedded inline
  • Print-optimised CSS with page-break controls
  • Linked Table of Contents
  • Pandoc-standard typography
  • Sidebar navigation (this sidebar)

Open any chapter directly in a browser, print to PDF, or host as GitHub Pages.

Citations

Content cites peer-reviewed literature, processor architecture manuals, and production system papers:

  • Intel SDM, AMD64 APM, ARM ARM, RISC-V Privileged Spec
  • ISCA, MICRO, ASPLOS, USENIX papers
  • IEEE-style references in every chapter
  • Minimum 8 references per chapter; AI chapters ≥ 12

Speculative claims about proprietary implementations are avoided.

Memory Management Units and TLBs — Architecture, Implementation, and AI Workloads